E. Wang of Imperial College and M. Abdelfattah of Cornell

LUTNet (2019)

abstract:

DNNs contain significant redundancy – weights and activations can be quantized down to binary values, without degrading model accuracy.

Network binarisation on FPGAs replaces resource-hungry multipliers with lightweight XNOR gates(in sync with VLSI undergrad course).

As FPGA’s building block K-LUT (K-input Look Up Table) can perform any K-input Boolean operation, there are more opportunities for mapping a binary network to FPGAs.

Exploitation of LUT flexibility allows far heavier pruning than possible, resulting in area saving while retaining performance.

to note:

the paper’s implementation of end-to-end hardware-software framework is work a close look.

details:

a BNN is first sparsified before its remaining XNORs are replaced with trainable K:1 Boolean operators – a process called logic expansion

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Logic Shrinkage for Efficient Inference (2022)

abstract:

a learned optimization of LUTNet, where K a priori, the number of inputs per LUT, must be specified.

Logic shrinkage, a fine-grained netlist pruning methodology let K to be learned for each LUT. By removing low-importance LUT inputs (pruning), accelerator efficiency is increased.

but

as can be seen from title, the FPGA Netlist Sparsity of LEARNED.

related work:

details: