Undergrad coursework project to add integer MAD (Multiply-add) operation to RISC-V. MAD operation is significant in its application to convolution operation.

Code Repo: https://github.com/dhjoo98/undergrad_RISCV

Following components were extended for implementation.

LLVM compiler

GCC assembler

RISC-V RTL

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LLVM

A modular set of compilers capable of compiling a variety of languages into various target architecture’s instructions – RISCV in my case

In order to have this modularity, LLVM employs various compilers for frontend lexer-parser and backend generator.

LLVM IR mediates between the front and backend, as LLVM Assembly (.ll).

LLVM Backend – ‘llc‘

Builds DAG from LLVM IR, performs optimization, then performs instruction selection.

Extension is applied here to add a new operator definition IMAD

GCC

Serves as assembler to create object file from assembly language.

Link object codes together into an executable

Extended is applied so that the correct register type can be used to create the correct instruction in a correct format.

RISC-V RTL

simulates a RISC-V processor, with precompiled instruction fed one-by-one.

Decoder – extend for IMAD support

Issue Unit – pipeline controller for IMAD

Muladder – provided to compute fast IMAD

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In a way, this is ‘cross-compilation’, because the target architecture was ‘RISC-V’ while the code was compiled on Linux VM running on Aarch64