As final project for KECE463 VLSI Design and Laboratory
We were to optimize the 2D DCT portion of the JPEG image compression process
Given performance threshold was PSNR(peak signal-to-noise ratio) of 29.0dB on 8 test images
Algorithm-level Optimization
Algorithm-level optimization was first tested on Matlab simulation to check if it doesn’t violate the performance threshold before RTL implementation.
I exploited the ‘Sensitivity Difference in frequency domain’, in which after transformation into frequency domain, the high frequency aspects of the image have no significant impact on the restored image.
Truncating the higher frequencies enabled reduction in memory and computation overhead.
Dataflow-level Optimization
Exploiting sensitivity difference still left a considerable leg room for further optimization
Dataflow-level optimization was also tested on Matlab simulation to check if it doesn’t violate the performance threshold before RTL implementation.
This level of optimization involved reducing the bit-width of DCT operands. (Roughly equal to using float instead of double)
Circuit-level Optimization
This level of optimization was applied straight to Verilog RTL implementation.
The same multiplier can be optimized with
- operand sharing
- using shift operations – reducing heavy additions
Performance
PSNR for all test images surpassed the threshold.
However, the quality itself of the restored image has more to be said: truncating the high frequency components have left vertical shadowy lines across all images.
Synthesis Result
After Verilog RTL implementation, Synopsys Design Compiler was used for synthesis:
Operating frequency: 100MHz
Though unable to compare with other students’ results, I think the A+ tells its tale.
RTL source code on my github!
Donghyeon Joo 
Leave a comment